The present invention relates to a variable gain amplifier.
Charge-coupled device (CCD) is the sensor of choice in modem imaging to convert photons into electrons, hence enabling the use of electronics for image processing. FIG. 1 shows typical analog front-end building blocks for a CCD signal processing channel. The CCD input signal 100 is received by a correlated double sampling circuit (CDS) 102 whose function is to extract the image content from the CCD signal 100 and remove the unwanted correlated noise component. A programmable gain amplifier (PGA) 104 amplifies the output of the CDS 102 before it gets converted to digital data by an analog-to-digital converter (ADC) 106. The gain of the PGA 104 can be programmed by providing a gain input 110 to the gain control circuit 112.
In reality, the circuit building blocks have offset, and such offset can reduce the dynamic range of the processing channel. In particular, any signal offset upstream of the PGA gets amplified by the PGA to a level related to the gain of the PGA, and hence seriously reduces the useful dynamic range of the PGA output and ADC. Such offset can come from the CCD signal, the CDS, or the input-referred offset of the PGA. For example, for an offset of 10 mV with a gain of 50xc3x97 in the PGA, the output-referred offset at the output of the PGA becomes 0.5V. This reduces the dynamic range of the PGA output and ADC by 0.5V, which is not acceptable in most integrated circuit design applications.
In order to address this problem, an offset correction is typically used. One way to provide an offset correction is to integrate the output of the PGA during the calibration interval (e.g., black pixel period) and subtract the accumulated error from the input of the PGA in a feedback fashion. The feedback adjusts the input of the PGA such that the output of the PGA is equal to the system""s xe2x80x9czeroxe2x80x9d reference during CCD""s black pixels. This scheme is shown in FIG. 2. In this figure, INT 200 refers to an integrator.
One problem with the scheme of FIG. 2 is that the time constant of the loop (PGA 104 and INT 200 loop) depends on the gain of the PGA 104. To keep the feedback loop stable and the noise of the xe2x80x9czeroxe2x80x9d reference low, the bandwidth of the loop must be kept low and constant, keeping the loop gain constant with the varying PGA gain. This can be accomplished by inserting another PGA in the feedback path with a reciprocal gain characteristic of the PGA in the forward path. We call this a reverse PGA (RPGA) 300, which is shown in FIG. 3.
The gain characteristics of the PGA, the RPGA and the loop are shown in the diagrams of FIG. 4. The PGA gain, the RPGA gain and the loop gain are each shown with respect to input gain. In terms of the dynamics of the loop, the order of RPGA 300 and INT 200 in the feedback path does not matter. The RPGA 300 can come before the INT 200 in the feedback path of the loop. There are, however, circuit level consequences that make the implementation of FIG. 3 a preferred embodiment.
There are two limitations with the implementations of FIGS. 2-3. First, INT 200 must have a large enough output range to handle any offset before PGA 104. Note that the offset correction removes the offset from the output of the PGA 104; this correction is accomplished by INT""s 200 providing the same offset (with opposite polarity) in the feedback loop. This can be a problem in a low supply (e.g.,  less than 3.0V) voltage environment. Second, PGA 104 must have a wide gain control range. Many CCD camera applications require a gain range of up to 40 dB (100xc3x97) with a maximum gain of 40 dB. This requires the PGA 104 to have an adequate bandwidth at the maximum gain, which increases the circuit""s size and power consumption. The circuit of FIG. 3 is particularly vulnerable to size and power consumption increases due to its use of two PGA blocks.
To avoid the limitations of the prior art, a CCD signal processing channel with split offset correction is offered. Dual integrators are used to correct offset from the CCD input to the digital output. One integrator is placed at the correlated double sampling circuit to remove the CCD""s offset as well as the CDS""s offset. A second integrator is placed after the PGA to remove the PGA""s offset as well as any uncorrected offset from the first offset correction. In an alternate embodiment, the second integrator can be placed after an analog digital converter (ADC) so that the integrator can operate entirely digitally. Alternatively, a digital PGA can be used in the channel. The signal from the CDS is converted by the ADC before it reaches the PGA and a digital PGA (DPGA) is used to produce a digital output. In an alternate embodiment, an analog PGA is used in combination with a DPGA. An ADC is placed at the output of the PGA which then provides the input for the digital DPGA. In this embodiment, gain control is offered for both the PGA and DPGA.
In the dual PGA, dual offset correction embodiment the first integrator is positioned at the correlated double sampling circuit and the second integrator is either positioned at the output of the PGA or at the output of the analog to digital converter.
In one embodiment, a pixel gain amplifier is used in combination with the CDS.